a) Field of the Invention
The present invention relates to a method of forming a multilayered wiring, for the manufacture of LSI or the like, and more particularly to such a method capable of preventing a cap metal layer of an under wiring Layer from being etched out completely, by forming a contact hole by a dry etching using a fluorine based etching gas after introducing a conductive material such as Al to the cap metal layer.
b) Description of the Related Art
A known conventional method of forming a multilayered wiring for LSI or the like is illustrated in FIG. 9. A lower wiring layer 2 is first formed on an insulating film 1, the lower wiring layer 2 having a laminated structure off a barrier metal layer 2a , Al or Al alloy layer 2b , and a cap metal layer 2c formed in this order from the bottom. Thereafter, an insulating film 3 is formed covering the lower wiring layer 2. A contact hole 3A is formed in the insulating film by a selective dry etching method. An upper wiring layer 4 is formed on the insulating film 3 and connected to the lower wiring layer 2 via the contact hole 3A.
The barrier metal layer 2a is used for providing a good ohmic contact with the surface of tile silicon substrate under the insulating film 1, and is made of a conductive material such as WSi.sub.2, MoSi.sub.2, and TiW. The barrier metal layer 2a is also used for preventing penetration of aluminum into silicon substrate during a heat treatment. The cap metal layer 2c is used for preventing a conduction defect (non-ohmic) to be caused by silicon nodules SN generated by precipitation of excessive silicon in silicide or Al alloy into the lower wiring layer 2b and filling the contact hole 3A, and is made of a conductive material such as WSi.sub.2, MoSi.sub.2, or TiW.
In the dry etching process of forming the contact hole 3A, a mixed gas (such as CHF.sub.3 /He/O.sub.2, and CF.sub.4 /CHF.sub.3 /Ar) containing a fluorine-based gas such as CHF.sub.3 is used as tile etching gas.
With the above-described conventional method, if the cap metal layer 2c is made of material subjected to etching by a fluorine-based plasma gas, the cap metal layer 2c reduces its thickness and may sometimes disappear from the area just under the contact hole 3A. Under this condition, if silicon nodules are formed in tile layer 2b under the contact hole, the conduction state between the wiring layer 4 and wiring layer 2 becomes insufficient.
In order to avoid such a case, it is conceivable to form the cap metal layer 2c sufficiently thick so that this layer 2c is not etched out completely. With this method, however, there occur the following two problems. (A) The step at the wiring layer becomes great, degrading the flatness on the substrate upper surface, and (B) if the Al or Al alloy 2b is made thin corresponding in amount to the increased thickness of the cap metal layer 2c, the wiring resistivity increases because the resistivity of the cap metal is higher than the Al or Al alloy layer 2b.
Another method of eliminating such problems is to form a silicon nitride layer under the insulating film 3 as an etching stopper, as described in, for example, Japanese Patent Laid-open Publication No.2-34818. In forming the contact hole 3A in the insulating film 3, made of a thin silicon nitride layer and thick silicon oxide film, the insulating film 3 is etched first under the condition of a faster etching speed of the silicon oxide than the silicon nitride, and then under the condition of a faster etching speed of the silicon nitride than the silicon oxide. In this manner, it is possible to shorten the time while the wiring layer surface is exposed to the etching atmosphere.
With this method, however, the following problems occur. (C) The number of processes required for forming an insulating film increases, and (D) the thickness of the cap metal layer also reduces corresponding in amount to the faster etching speed of the silicon nitride at the second etching step.